---------------AND Gate Main File------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test is
Port(
a: in std_logic;
b: in std_logic;
c: out std_logic
);
end test;
architecture Behavioral of test is
begin
c <= a and b;
end Behavioral;
---------------AND Gate TB File------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_tb is
end test_tb;
architecture Behavioral of test_tb is
--Component name and entity's name must be same ports must be same
component test is
Port (
A,B:in std_logic;
C: out std_logic
);
end component;
--inputs
signal a: std_logic:= '0';
signal b: std_logic:= '0';
--outputs
signal c : std_logic;
begin
uut: test PORT MAP(a=>a,b=>b,c=>c);
--Stimulus Process
stim_proc:process
begin
wait for 10ns;
a<='1';
b<='0';
wait for 10ns;
a<='0';
b<='1';
wait for 10ns;
a<='0';
b<='0';
wait for 10ns;
a<='1';
b<='1';
wait for 10ns;
end process;
end Behavioral;