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half adder code in VHDL

Farah Farooq answered on September 26, 2022 Popularity 7/10 Helpfulness 7/10

answer half adder code in VHDL

half adder code in VHDL

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---------------half-adder Main File ------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity test is
     Port(
         a: in std_logic;
         b: in std_logic;
         sum: out std_logic;
         carry: out std_logic
     );
end test;

architecture Behavioral of test is
begin

    sum <= a xor b;
    carry <= a and b;

end Behavioral;

---------------half-adder TB File------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_tb is
end test_tb;

architecture Behavioral of test_tb is

--Component name and entity's name must be same ports must be same   
    component test is
      Port (
        a,b:in std_logic;
        sum: out std_logic;
      carry: out std_logic
      );
    end component;
    
    --inputs
    signal a: std_logic:= '0';
    signal b: std_logic:= '0';
   
    --outputs
    signal sum : std_logic;
    signal carry : std_logic;
    
    begin
    uut: test PORT MAP(a=>a,b=>b,sum=>sum,carry=>carry);
    
    --Stimulus Process
    stim_proc:process
    begin
    wait for 10ns;
    a<='1';
    b<='0';
    wait for 10ns;
    a<='0';
    b<='1';
    wait for 10ns;
    a<='0';
    b<='0';
    wait for 10ns;
    a<='1';
    b<='1';
    wait for 10ns;
    end process;
    
end Behavioral;

Popularity 7/10 Helpfulness 7/10 Language whatever

Source: Grepper

Tags: vhdl whatever

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Contributed on Sep 26 2022

Farah Farooq

0 Answers Avg Quality 2/10

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half adder code in VHDL

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