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module shift_right_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in);
always @ (sig_in)
sig_out = {sig_in[31], sig_in[31], sig_in[31], sig_in[31: 3]};
endmodule
module t_shift_right_by_3 ();
wire [31: 0] sig_out_V1995;
wire [31: 0] sig_out_V2001;
reg [31: 0] sig_in;
shift_right_by_3_V1995 M1 (sig_out_V1995, sig_in);
integer k;
initial #1000 $finish;
initial begin
sig_in = 32'hf000_0000;
#100 sig_in = 32'h8fff_ffff;
#500 sig_in = 32'h0fff_ffff;
end
endmodule