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module module_name #(parameter_list) (input_list, output_list);
// Port declarations, parameter declarations, and internal signal declarations
// Logic and behavior of the module
endmodule
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module Mux2to1 #(parameter SEL_WIDTH = 1) (
input logic A,
input logic B,
input logic [SEL_WIDTH-1:0] Sel,
output logic Y
);
always_comb begin
case (Sel)
2'b00: Y = A;
2'b01: Y = B;
default: Y = 1'bx; // Output undefined for other cases
endcase
end
endmodule