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Generate a vhdl code for 4-bit full adder

Ayomikun faluyi answered on September 13, 2023 Popularity 1/10 Helpfulness 1/10

answer Generate a vhdl code for 4-bit full adder

Generate a vhdl code for 4-bit full adder

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder4Bit is
    Port (
        A, B, Cin: in STD_LOGIC_VECTOR(3 downto 0);
        Sum, Cout: out STD_LOGIC_VECTOR(3 downto 0)
    );
end FullAdder4Bit;

architecture Behavioral of FullAdder4Bit is
begin
    process(A, B, Cin)
        variable carry: STD_LOGIC := '0';
    begin
        for i in 0 to 3 loop
            Sum(i) <= A(i) XOR B(i) XOR carry;
            carry := (A(i) AND B(i)) OR (B(i) AND carry) OR (A(i) AND carry);
        end loop;
        Cout <= carry & '0'; -- Extending carry to the fourth bit
    end process;
end Behavioral;

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Contributed on Sep 13 2023

Ayomikun faluyi

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Generate a vhdl code for 4-bit full adder

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